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INTEGRATED CIRCUITS
DATA SHEET
PCF2104x LCD controller/driver
Product specification Supersedes data of 1997 Apr 01 File under Integrated Circuits, IC12 1997 Dec 16
Philips Semiconductors
Product specification
LCD controller/driver
CONTENTS 1 2 3 3.1 3.2 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 9 9.1 9.2 9.3 9.3.1 9.3.2 FEATURES APPLICATIONS GENERAL DESCRIPTION Packages Available types ORDERING INFORMATION BLOCK DIAGRAM PINNING PIN FUNCTIONS RS: register select (parallel control) R/W: read/write (parallel control) E: data bus clock (parallel control) DB0 to DB7: data bus (parallel control) C1 to C60: column driver outputs R1 to R32: row driver outputs VLCD: LCD power supply OSC: oscillator SCL: serial clock line SDA: serial data line SA0: address pin T1: test pad FUNCTIONAL DESCRIPTION LCD bias voltage generator Oscillator External clock Power-on reset Registers Busy Flag Address Counter (AC) Display data RAM (DDRAM) Character generator ROM (CGROM) Character generator RAM (CGRAM) Cursor control circuit Timing generator LCD row and column drivers Programming of MUX 1 : 16 displays with PCF2104x Programming of MUX 1 : 32 displays with PCF2104x Reset function INSTRUCTIONS Clear display Return home Entry mode set I/D S 9.4 9.4.1 9.4.2 9.4.3 9.5 9.6 9.6.1 9.6.2 9.7 9.8 9.9 9.10 9.11 10 11 11.1 11.2 11.3 11.4 11.5 11.6 12 13 14 15 16 17 17.1 17.2 17.3 17.4 17.5 18 19 20 21
PCF2104x
Display on/off control D C B Cursor/display shift Function set DL (parallel mode only) N, M Set CGRAM address Set DDRAM address Read busy flag and address Write data to CGRAM or DDRAM Read data from CGRAM or DDRAM INTERFACE TO MICROCONTROLLER (PARALLEL INTERFACE) INTERFACE TO MICROCONTROLLER (I2C-BUS INTERFACE) Characteristics of the I2C-bus Bit transfer Start and stop conditions System configuration Acknowledge I2C-bus protocol LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS TIMING DIAGRAMS APPLICATION INFORMATION 8-bit operation, 2 x 12 display using internal reset 4-bit operation, 2 x 12 display using internal reset 8-bit operation, 2 x 24 display I2C operation, 2 x 12 display Initializing by instruction BONDING PAD LOCATIONS DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1997 Dec 16
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Philips Semiconductors
Product specification
LCD controller/driver
1 FEATURES
PCF2104x
but does not contain the high voltage generator of that device. The PCF2104x is optimized for chip-on-glass applications. The `x' in `PCF2104x' represents a specific letter code for a character set in the character generator ROM (CGROM). Two standard character sets are currently available, specified by the letters `C' and `L' (see Figs 5 and 6). Other character sets are available on request. The PCF2104x is a low-power CMOS LCD controller and driver, designed to drive a split screen dot matrix LCD display of 1 or 2 lines by 24 characters or 2 or 4 lines by 12 characters with a 5 x 8 dot format. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages which results in a minimum of external components and lower system power consumption. To allow partial VDD shutdown the ESD protection system of the SCL and SDA pins does not use a diode connected to VDD. The chip contains a character generator and displays alphanumeric and kana characters. The PCF2104x interfaces to most microcontrollers via a 4 or 8-bit bus, or via the 2-wire I2C-bus. 3.1 Packages
* Single chip LCD controller/driver * 1 or 2-line display of up to 24 characters per line, or 2 or 4 lines of up to 12 characters per line * 5 x 7 character format plus cursor; 5 x 8 for kana (Japanese syllabary) and user-defined symbols * On-chip: - generation of intermediate LCD bias voltages - oscillator requires no external components (external clock also possible) * Display data RAM: 80 characters * Character generator ROM: 240 characters * Character generator RAM: 16 characters * 4 or 8-bit parallel bus or 2-wire I2C-bus interface * CMOS/TTL compatible * 32 row, 60 column outputs * MUX rates 1 : 32 and 1 : 16 * Uses common 11 code instruction set * Logic supply voltage range, VDD - VSS: 2.5 to 6 V * Display supply voltage range, VDD - VLCD: 3.5 to 9 V * Low power consumption. * I2C-bus address: 011101 SA0. 2 APPLICATIONS
* PCF2104xU/2; chip with bumps in tray * PCF2104xU/7; chip with bumps on tape. For further details see Chapter 18. 3.2 Available types
* Telecom equipment * Portable instruments * Point-of-sale terminals. 3 GENERAL DESCRIPTION
* PCF2104CU/x: character set `C' in CGROM * PCF2104LU/x: character set `L' in CGROM * PCF2104NU/x: character set `N' in CGROM.
The PCF2104x integrated circuit is similar to the PCF2114x (described in the "PCF2116 family" data sheet) 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF2104CU/2 PCF2104CU/7 PCF2104LU/2 PCF2104LU/7 PCF2104NU/2 PCF2104NU/7 1997 Dec 16 - - - - - - chip with bumps in tray chip with bumps on tape chip with bumps in tray chip with bumps on tape chip with bumps in tray chip with bumps on tape 3 DESCRIPTION VERSION - - - - - -
Philips Semiconductors
Product specification
LCD controller/driver
5 BLOCK DIAGRAM
PCF2104x
C1 to C60
handbook, full pagewidth
R1 to R32 5-20 81-96 32 ROW DRIVERS 32 SHIFT REGISTER 32-BIT
80-21 60 111 BIAS VOLTAGE GENERATOR COLUMN DRIVERS 6 60
V LCD
DATA LATCHES 60 SHIFT REGISTER 5 x 12-bit 5 CURSOR + DATA CONTROL 2 CHARACTER GENERATOR RAM (CGRAM) 16 CHARACTERS 5 CHARACTER GENERATOR ROM (CGROM) 240 CHARACTERS
PCF2104x
VDD V SS
4
OSCILLATOR
1
OSC
T1
101
8 DISPLAY DATA RAM (DDRAM) 80 CHARACTERS 7 ADDRESS COUNTER (AC) 7 INSTRUCTION DECODER 8 DATA REGISTER (DR) 8 7 BUSY FLAG 8 INSTRUCTION REGISTER (IR) 8 I/O BUFFER 4 109-106 DB0 to DB3 105-102 DB4 to DB7 E 4 98 100 R/W 99 RS 97 SCL 7
TIMING GENERATOR
DISPLAY ADDRESS COUNTER
POWER - ON RESET
110 SDA
3
MGC627
SA0
Fig.1 Block diagram.
1997 Dec 16
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Philips Semiconductors
Product specification
LCD controller/driver
6 PINNING SYMBOL OSC VDD SA0 VSS R8 to R5 R32 to R29 R24 to R17 C60 to C1 R9 to R16 R25 to R28 R1 to R4 SCL E RS R/W T1 DB7 to DB0 SDA VLCD 7 7.1 PIN FUNCTIONS RS: register select (parallel control) FFC PAD 1 2 3 4 5 to 8 9 to12 13 to 20 21 to 80 81 to 88 89 to 92 93 to 96 97 98 99 100 101 102 to 109 110 111 TYPE I P I P O O O O O O O I I I I I I/O I/O I 7.4
PCF2104x
DESCRIPTION oscillator/external clock input logic supply voltage I2C-bus address pin input ground LCD row driver outputs LCD row driver outputs LCD row driver outputs LCD column driver outputs LCD row driver outputs LCD row driver outputs LCD row driver outputs I2C-bus serial clock input data bus clock input register select input read/write input test pad input 8-bit bidirectional data bus input/output I2C-bus serial data input/output LCD supply voltage input DB0 to DB7: data bus (parallel control)
RS selects the register to be accessed for read and write when the device is controlled by the parallel interface. RS = logic 0 selects the instruction register for write and the Busy Flag and Address Counter for read. RS = logic 1 selects the data register for both read and write. There is an internal pull-up on pin RS. 7.2 R/W: read/write (parallel control)
The bidirectional, 3-state data bus transfers data between the system controller and the PCF2104x. DB7 may be used as the Busy Flag, signalling that internal operations are not yet completed. In 4-bit operations the 4 higher order lines DB4 to DB7 are used; DB0 to DB3 must be left open circuit. There is an internal pull-up on each of the data lines. Note that these pins must be left open circuit when I2C-bus control is used. 7.5 C1 to C60: column driver outputs
R/W selects either the read (R/W = logic 1) or write (R/W = logic 0) operation when control is by the parallel interface. There is an internal pull-up on this pin. 7.3 E: data bus clock (parallel control)
These pins output the data for pairs of columns. This arrangement permits optimized chip-on-glass (COG) layout for 4-line by 12 characters. 7.6 R1 to R32: row driver outputs
The E pin is set HIGH to signal the start of a read or write operation when the device is controlled by the parallel interface. Data is clocked in or out of the chip on the negative edge of the clock. Note that this pin must be tied to logic 0 (VSS) when I2C-bus control is used.
These pins output the row select waveforms to the left and right halves of the display. 7.7 VLCD: LCD power supply
Negative power supply for the liquid crystal display.
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Philips Semiconductors
Product specification
LCD controller/driver
7.8 OSC: oscillator 8.2 Oscillator
PCF2104x
When the on-chip oscillator is used, this pin must be connected to VDD. An external clock signal, if used, is input at this pin. 7.9 SCL: serial clock line
The on-chip oscillator provides the clock signal for the display system. No external components are required. Pin OSC must be connected to VDD. 8.3 External clock
Input for the I2C-bus clock signal. 7.10 SDA: serial data line
Input/output for the I2C-bus data line. 7.11 SA0: address pin
If an external clock is to be used, it must be input at pin OSC. The resulting display frame frequency is given by fframe = 12304fosc. A clock signal must always be present, otherwise the LCD may be frozen in a DC state. 8.4 Power-on reset
The hardware sub-address line is used to program the device sub-address for 2 different PCF2104xs on the same I2C-bus. 7.12 T1: test pad
The Power-on reset block initializes the chip after power-on or power failure. 8.5 Registers
Must be connected to VSS. Not user accessible. 8 8.1 FUNCTIONAL DESCRIPTION (see Fig.1) LCD bias voltage generator
The PCF2104x has two 8-bit registers, an instruction register (IR) and a data register (DR). The register select signal (RS) determines which register will be accessed. The instruction register stores instruction codes such as display clear and cursor shift, and address information for the Display Data RAM (DDRAM) and Character Generator RAM (CGRAM). The instruction register can be written to, but not read from, by the system controller. The data register temporarily stores data to be read from the DDRAM and CGRAM. When reading, data from the DDRAM or CGRAM (corresponding to the address in the Address Counter) is written to the data register prior to being read by the `Read data' instruction. 8.6 Busy Flag
The intermediate bias voltages for the LCD display are also generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system power consumption. The optimum levels depend on the multiplex rate and are selected automatically when the number of lines in the display is defined. The optimum value of VOP depends on the multiplex rate, the LCD threshold voltage (Vth) and the number of bias levels. The relationships are given in Table 1. Using a 5-level bias scheme for 1 : 16 MUX rate allows VOP < 5 V for most LCD liquids. The effect on the display contrast is negligible. Table 1 MUX RATE 1 : 16 1 : 32 Optimum values for VOP NUMBER OF BIAS LEVELS 5 6 VOP/Vth 3.67 5.19 DISCRIMINATION Von/Voff 1.277 1.196
The Busy Flag indicates the free/busy status of the PCF2104x. Logic 1 indicates that the chip is busy and further instructions will not be accepted. The Busy Flag is output at pin DB7 when RS = logic 0 and R/W = logic 1. Instructions should only be written after checking that the Busy Flag is at logic 0 or waiting for the required number of clock cycles.
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Philips Semiconductors
Product specification
LCD controller/driver
8.7 Address Counter (AC) 8.10
PCF2104x
Character generator RAM (CGRAM)
The Address Counter assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the instructions `Set CGRAM address' and `Set DDRAM address'. After a read/write operation the Address Counter is automatically incremented or decremented by 1. The Address Counter contents are output to the bus (DB0 to DB6) when RS = logic 0 and R/W = logic 1. 8.8 Display data RAM (DDRAM)
Up to 16 user-defined characters may be stored in the character generator RAM. The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM (see Fig.5). Figure 8 shows the addressing principle for the CGRAM. 8.11 Cursor control circuit
The DDRAM stores up to 80 characters of display data, represented by 8-bit character codes. DDRAM locations not used for storing display data can be used as general purpose RAM. The basic DDRAM-to-display mapping scheme is shown in Fig.2. With no display shift, the characters represented by the codes in the first 12 or 24 RAM locations, starting at address 00 in line 1, are displayed. Subsequent lines display data starting at addresses 20, 40, or 60 Hex. Figures 3 and 4 show the DDRAM-to-display mapping scheme when the display is shifted. The address range for a 1-line display is 00 to 4F; for a 2-line display from 00 to 27 (line 1) and 40 to 67 (line 2); for a 4-line display from 00 to 13, 20 to 33, 40 to 53 and 60 to 73 for lines 1, 2, 3 and 4 respectively. For 2 and 4-line displays the end address of one line and the start address of the next line are not consecutive. When the display is shifted each line wraps around independently of the others (see Figs 3 and 4). When data is written to the DDRAM wrap-around occurs from 4F to 00 in 1-line mode and from 27 to 40 and 67 to 00 in 2-line mode; from 13 to 20, 33 to 40, 53 to 60 and 73 to 00 in 4-line mode. 8.9 Character generator ROM (CGROM)
The cursor control circuit generates the cursor (underline and/or character blink as shown in Fig.9) at the DDRAM address contained in the Address Counter. When the Address Counter contains the CGRAM address the cursor will be inhibited. 8.12 Timing generator
The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses. 8.13 LCD row and column drivers
The PCF2104x contains 32 row and 60 column drivers, which connect the appropriate LCD bias voltages in sequence to the display, in accordance with the data to be displayed. The bias voltages and the timing are selected automatically when the number of lines in the display is selected. Figures 10 and 11 show typical waveforms. In the 1-line mode (1 : 16) the row outputs are driven in pairs: R1/R17, R2/R18 for example. This allows the output pairs to be connected in parallel, thereby providing greater drive capability. Unused outputs should be left unconnected.
The character generator ROM generates 240 character patterns in 5 x 8 dot format from 8-bit character codes. Figures 5 and 6 show the character sets currently available.
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
Display handbook, 4 columns Position (decimal)
1
2
3
4
5
22 23 24
non-displayed DDRAM addresses
4C 4D 4E 4F
00 01 02 03 04
15 16 17 18 19
DDRAM Address (hex)
1-line display non-displayed DDRAM address
00 01 02 03 04 15 16 17 18 19 24 25 26 27
DDRAM Address (hex)
line 1
40 41 42 43 44
55 56 57 58 59
64 65 66 67
MLA792
line 2
2-line display
handbook, 4 columns
non-displayed DDRAM addresses 2 3 4 5 6 7 8 9 10 11 12 line 1
1
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33
line 2
DDRAM Address (hex)
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53
line 3
60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73
line 4
4 line display
MLA793
Fig.2 DDRAM-to-display mapping; no shift (PCF2104x).
1997 Dec 16
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
Display Position (decimal) DDRAM Address (hex)
1
23
4
5
22 23 24
14 15 16
Display Position (decimal) DDRAM Address (hex)
line 1
1
23
4
5
22 23 24
16 17 18
4F 00 01 02 03
01 02 03 04 05
1-line display
1-line display
27 00 01 02 03
14 15 16
01 02 03 04 05
16 17 18
line 1
DDRAM Address (hex)
67 40 41 42 43
54 55 56
MLA802
line 2
DDRAM Address (hex)
41 42 43 44 45
56 57 58
MLA815
line 2
2-line display
2-line display
1234567
8 9 10 11 12 line 1
12
3 4 5 6 7 8 9 10 11 12 line 1
13 00 01 02 03 04 05 06 07 08 09 0A
01 02 03 04 05 06 07 08 09 0A 0B 0C
33 20 21 22 23 24 25 26 27 28 29 2A
line 2 DDRAM Address (hex)
21 22 23 24 25 26 27 28 29 2A 2B 2C
line 2
DDRAM Address (hex)
53 40 41 42 43 44 45 46 47 48 49 4A
line 3
41 42 43 44 45 46 47 48 49 4A 4B 4C
line 3
73 60 61 62 63 64 65 66 67 68 69 6A
line 4
61 62 63 64 65 66 67 68 69 6A 6B 6C
line 4
MLA816
4-line display
MLA803
4-line display
Fig.3
DDRAM-to-display mapping; right shift (PCF2104x).
Fig.4
DDRAM-to-display mapping; left shift (PCF2104x).
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
handbook, full pagewidth upper
lower 4 bits xxxx
4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
CG RAM 1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
MLB895
Fig.5 Character set `C' in CGROM; PCF2104C.
1997 Dec 16
10
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
handbook, full pagewidth upper
lower 6 bits xxxx
4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
CG RAM 1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
MGC629
Fig.6 Character set `L' in CGROM; PCF2104L.
1997 Dec 16
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
handbook, full pagewidth upper
lower 4 bits xxxx
4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
CG RAM 1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
MGM134
Fig.7 Character set `N' in CGROM; PCF2104N.
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
handbook, full pagewidth
character codes (DDRAM data) 6 5 4 3 2 1 lower order bits 0 0 0 0 0 0 0 6 5
CGRAM address 4 3 2 1 lower order bits 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 higher order bits
character patterns (CGRAM data) 4 3 2 1 0
7
higher order bits 0 0 0
higher order bits 0 0
lower order bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 character pattern example 2 0 0 0 0 character pattern example 1 cursor position
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
MGA800 - 1
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6. CGRAM address bits 0 to 2 designate character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the cursor. Data in the 8th line will appear in the cursor position. Character pattern column positions correspond to CGRAM data bits 0 to 4; bit 4 being at the left end, as shown in the figure. CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds to selection for display. Only bits 0 to 5 of the CGRAM address are set by the `Set CGRAM address' instruction. Bit 6 can be set using the `Set DDRAM address' instruction or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the `Read Busy Flag and address' instruction.
Fig.8 Relationship between CGRAM addresses, data and display patterns.
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
cursor 5 x 7 dot character font alternating display
MGA801
cursor display example
blink display example
Fig.9 Cursor and blink display examples.
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
handbook, full pagewidth
frame n
frame n 1
state 1 (ON) state 2 (ON)
ROW 1
VDD V2 V3 /V4 V5 V LCD VDD V2
ROW 9
V3 /V4 V5 V LCD VDD V2 V3 /V4 V5 V LCD VDD V2
1-line display (1:16)
ROW 2
COL 1
V3 /V4 V5 V LCD VDD V2 V3 /V4 V5 V LCD VOP
COL 2
0.25 VOP state 1 0 V 0.25 VOP VOP VOP
0.25 VOP state 2 0 V 0.25 VOP VOP
MGA802 - 1
123
16 1 2 3
16
Fig.10 Typical LCD waveforms; 1-line mode.
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
handbook, full pagewidth
frame n V DD V2 V3 V4 V5 V LCD V DD V2 V3 V4 V5 V LCD V DD V2 V3 V4 V5 V LCD V DD V2 V3 V4 V5 V LCD V DD V2 V3 V4 V5 V LCD
frame n 1
state 1 (ON) state 2 (ON)
ROW 1
ROW 9
ROW 2
2-line display (1:32)
COL 1
COL 2
VOP
state 1
0.15 VOP 0V 0.15 VOP
VOP VOP
state 2
0.15 VOP 0V 0.15 VOP
VOP
MGA803 - 1
123
32 1 2 3
32
Fig.11 Typical LCD waveforms; 2-line mode.
1997 Dec 16
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Philips Semiconductors
Product specification
LCD controller/driver
8.14 Programming of MUX 1 : 16 displays with PCF2104x
PCF2104x
Using the `Function set' instruction, M and N are set to 0, 0 (respectively). Figures 12, 13 and 14 show the DDRAM addresses of the display characters. The second row of each table corresponds to either the right half of a 1-line display or to the second line of a 2-line display. Wrap around of data during display shift or when writing data is non-standard.
The PCF2104x can be used in the following ways: * 1-line mode to drive a 2-line display * 2 x 12 characters with MUX rate 1 : 16, resulting in better contrast. The internal data flow of the chip is optimized for this purpose.
handbook, full pagewidth
display position DDRAM address
1 00
2 01
3 02
4 03
5 04
6 05
7 06
8 07
9 08
10 09
11 0A
12 0B
display position DDRAM address
13 0C
14 0D
15 0E
16 0F
17 10
18 11
19 12
20 13
21 14
22 15
23 16
24 17
MLB899
Fig.12 DDRAM-to-display mapping; no shift (PCF2104x).
handbook, full pagewidth
display position DDRAM address
1 4F
2 00
3 01
4 02
5 03
6 04
7 05
8 06
9 07
10 08
11 09
12 0A
display position DDRAM address
13 0B
14 0C
15 0D
16 0E
17 0F
18 10
19 11
20 12
21 13
22 14
23 15
24 16
MLB900
Fig.13 DDRAM-to-display mapping; right shift (PCF2104x).
handbook, full pagewidth
display position DDRAM address
1 01
2 02
3 03
4 04
5 05
6 06
7 07
8 08
9 09
10 0A
11 0B
12 0C
display position DDRAM address
13 0D
14 0E
15 0F
16 10
17 11
18 12
19 13
20 14
21 15
22 16
23 17
24 18
MLB901
Fig.14 DDRAM-to-display mapping; left shift (PCF2104x).
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Philips Semiconductors
Product specification
LCD controller/driver
8.15 Programming of MUX 1 : 32 displays with PCF2104x 9 INSTRUCTIONS
PCF2104x
To drive a 2-line by 24 characters MUX 1 : 32 display, use instruction `Function set' to set M, N to 0, 1 (respectively). To drive a 4-line by 12 characters MUX 1:32 display, use instruction `Function set' to set M, N to 1, 1 (respectively). 8.16 Reset function
The PCF2104 automatically initializes (resets) when power is turned on. The state after reset is given in Table 2. Table 2 STEP 1 2 Display clear. Function set: DL = 1: 8-bit interface M, N = 0 1-line display G = 0: not used 3 Display on/off control: D = 0: display off C = 0: cursor off; B = 0: blink off; 4 Entry mode set: I/D = 1: +1 (increment) G = 0: not used 5 Default address pointer to DDRAM. The Busy Flag (BF) indicates the busy state (BF = logic 1) until initialization ends. The busy state lasts 2 ms. The chip may also be initialized by software. See Tables 10 and 11. I2C-bus interface reset. State after reset DESCRIPTION
Only two PCF2104x registers, the instruction register (IR) and the data register (DR) can be directly controlled by the microcontroller. Before internal operation, control information is stored temporarily in these registers to allow interface to various types of microcontrollers which operate at different speeds or to allow interfacing to peripheral control ICs. The PCF2104x operation is controlled by the instructions shown in Table 3 together with their execution time. Details are explained in subsequent sections. Instructions are of 4 categories, those that: 1. Designate PCF2104x functions such as display format, data length, etc. 2. Set internal RAM addresses 3. Perform data transfer with internal RAM 4. Others. In normal use, category 3 instructions are used most frequently. However, automatic incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write lessens the microcontroller program load. The display shift in particular can be performed concurrently with display data write, thus enabling the designer to develop systems in minimum time with maximum programming efficiency. During internal operation, no instruction other than the Busy Flag/address read instruction will be executed. Because the Busy Flag is set to logic 1 while an instruction is being executed, it is advisable to ensure that the flag it is at logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in Table 3. An instruction sent while the Busy Flag is HIGH will not be executed.
6
1997 Dec 16
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Philips Semiconductors
Table 3
Instructions (note 1)
LCD controller/driver
INSTRUCTION NOP Clear display Return home
RS 0 0 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 No operation.
DESCRIPTION
REQUIRED CLOCK CYCLES(2) 0 165 3
Clears entire display and sets DDRAM address 0 in Address Counter. Sets DDRAM address 0 in Address Counter Also returns shifted display to original position DDRAM contents remain unchanged. Sets cursor move direction and specifies shift of display. These operations are performed during data write and read. Sets entire display on/off (D), cursor on/off (C) and blink of cursor position character (B). Moves cursor and shifts display without changing DDRAM contents. Sets interface data length (DL), number of display lines (N, M) and voltage generator control (G). Sets CGRAM address. Sets DDRAM address. Reads Busy Flag (BF) indicating internal operation is being performed and reads Address Counter contents. Reads data from CGRAM or DDRAM. Writes data to CGRAM or DDRAM.
Entry mode set
0
0
0
0
0
0
0
1
I/D
S
3
Display control Cursor/display shift Function set
0 0 0
0 0 0
0 0 0
0 0 0
0 0 1
0 1 DL
1 S/C N
D R/L M
C 0 G
B 0 0
3 3 3
Set CGRAM address Set DDRAM address Read busy flag and address Read data Write data Notes
0 0 0
0 0 1
0 1 BF
1
ACG ADD AC
3 3 0
1 1
1 0
read data write data
3 3
Product specification
1. In the I2C-bus mode the DL bit is don't care. 8-bit mode is assumed. In the I2C-bus mode a control byte is required when RS or R/W is changed; control byte: Co, RS, R/W, 0, 0, 0, 0, 0; command byte: DB7 to DB0. 1 2. Example: fosc = 150 kHz, T cy = -------- = 6.67 s; 3 cycles = 20 s, 165 cycles = 1.1 ms. f osc
PCF2104x
Philips Semiconductors
Product specification
LCD controller/driver
Table 4 BIT I/D S D C B S/C R/L DL N (M = 0) N (M = 1) BF Co decrement display freeze display off cursor off character at cursor position does not blink cursor move left shift 4 bits 2 line x 12 characters; MUX 1 : 16 reserved end of internal operation last control byte, only data bytes to follow Command bit identities LOGIC 0 increment display shift display on cursor on character at cursor position blinks display shift right shift 8 bits 2 lines x 24 characters; MUX 1 : 32 4 lines x 12 characters; MUX 1 : 32 internal operation in progress LOGIC 1
PCF2104x
next two bytes are a data byte and another control byte
RS
R/W
E
DB7
IR7
IR3
BF
AC3
DR7
DR3
DB6
IR6
IR2
AC6
AC2
DR6
DR2
DB5
IR5
IR1
AC5
AC1
DR5
DR1
DB4
IR4 instruction write
IR0
AC4
AC0
DR4
DR0
busy flag and address counter read
data register read
MGA804
Fig.15 4-bit transfer example.
1997 Dec 16
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
RS
R/W
E
internal
internal operation
DB7
IR7
IR3
busy
AC3
not busy
AC3
D7
D3
instruction write
busy flag check
busy flag check
instruction write
MGA805
IR7, IR3: instruction 7th bit, 3rd bit. AC3: Address Counter 3rd bit.
Fig.16 An example of 4-bit data transfer timing sequence.
RS
R/W
E
internal
internal operation
DB7
data instruction write
busy busy flag check
busy busy flag check
not busy busy flag check
data instruction write
MGA806
Fig.17 Example of Busy Flag check timing sequence.
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Philips Semiconductors
Product specification
LCD controller/driver
9.1 Clear display 9.4.2 C
PCF2104x
`Clear display' writes space code 20 (hexadecimal) into all DDRAM addresses (the character pattern for character code 20 must be a blank pattern), sets the DDRAM Address Counter to logic 0 and returns the display to its original position if it was shifted. Consequently, the display disappears and the cursor or blink position goes to the left edge of the display (the first line if 2 or 4 lines are displayed) and sets the entry mode to I/D = logic 1 (increment mode). S of entry mode does not change. The instruction `Clear display' requires extra execution time. This may be allowed for by checking the Busy Flag (BF) or by waiting until 2 ms has elapsed. The latter must be applied where no read-back options are foreseen, as in some chip-on-glass (COG) applications. 9.2 Return home
The cursor is displayed when C = logic 1 and inhibited when C = logic 0. Even if the cursor disappears, the display functions I/D, etc. remain in operation during display data write. The cursor is displayed using 5 dots in the 8th line (see Fig.9). 9.4.3 B
The character indicated by the cursor blinks when B = logic 1. The blink is displayed by switching between display characters and all dots on with a period of 1 second when fosc = 150 kHz (see Fig.9). At other clock frequencies the blink period is equal to 150 kHz/fosc. The cursor and the blink can be set to display simultaneously. 9.5 Cursor/display shift
`Return home' sets the DDRAM Address Counter to logic 0 and returns the display to its original position if it was shifted. DDRAM contents do not change. The cursor or blink position goes to the left of the display (the first line if 2 or 4 lines are displayed). I/D and S of entry mode do not change. 9.3 9.3.1 Entry mode set I/D
When I/D = logic 1 (0) the DDRAM or CGRAM address increments (decrements) by 1 when data is written to or read from the DDRAM or CGRAM. The cursor or blink position moves to the right when incremented and to the left when decremented. The cursor and blink are inhibited when the CGRAM is accessed. 9.3.2 S
`Cursor/display shift' moves the cursor position or the display to the right or left without writing or reading display data. This function is used to correct a character or move the cursor through the display. In 2 or 4-line displays, the cursor moves to the next line when it passes the last position of the line (40 or 20 decimal). When the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. The Address Counter (AC) content does not change if the only action performed is shift display, but increments or decrements with the cursor shift. 9.6 9.6.1 Function set DL (PARALLEL MODE ONLY)
When S = logic 1, the entire display shifts either to the right (I/D = logic 0) or to the left (I/D = logic 1) during a DDRAM write. Consequently, it looks as if the cursor stands still and the display moves. The display does not shift when reading from the DDRAM, or when writing to or reading from the CGRAM. When S = logic 0 the display does not shift. 9.4 9.4.1 Display on/off control D
Sets interface data width. Data is sent or received in bytes (DB7 to DB0) when DL = logic 1 or in two nibbles (DB7 to DB4) when DL = logic 0. When 4-bit width is selected, data is transmitted in two cycles using the parallel bus(1). Function set from I2C-bus interface: DL bit can not bet set to logic 0 from the I2C-bus interface. If bit DL has been set to logic 0 via the parallel bus, programming via the I2C-bus interface is complicated. 9.6.2 N, M
Sets number of display lines.
(1) In a 4-bit application DB3 to DB0 are left open (internal pull-ups). Hence in the first function set instruction after power-on G and H are set to 1. A second function set must then be sent (2 nibbles) to set G and H to their required values.
The display is on when D = logic 1 and off when D = logic 0. Display data in the DDRAM is not affected and can be displayed immediately by setting D to logic 1.
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Philips Semiconductors
Product specification
LCD controller/driver
9.7 Set CGRAM address 9.11
PCF2104x
Read data from CGRAM or DDRAM
`Set CGRAM address' sets bits 0 to 5 of the CGRAM address (ACG in Table 3) into the Address Counter (binary A[5] to A[0]). Data can then be written to or read from the CGRAM. Only bits 0 to 5 of the CGRAM address are set by the `Set CGRAM address' instruction. Bit 6 can be set using the `Set DDRAM address' instruction or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the `Read busy flag and address' instruction. 9.8 Set DDRAM address
Reads binary 8-bit data D[7] to D[0] from the CGRAM or DDRAM. The most recent `Set address' instruction determines whether the CGRAM or DDRAM is to be read. The `Read data' instruction gates the content of the data register (DR) to the bus while E = HIGH. After E goes LOW again, internal operation increments (or decrements) the AC and stores RAM data corresponding to the new AC into the DR. Remark: the only three instructions that update the data register (DR) are: * `Set CGRAM address' * `Set DDRAM address' * `Read data' from CGRAM or DDRAM. Other instructions (e.g. `Write data, `Cursor/display shift', `Clear display', `Return home') will not modify the data register content. 10 INTERFACE TO MICROCONTROLLER (PARALLEL INTERFACE) The PCF2104x can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. In the 8-bit mode data is transferred as 8-bit bytes using the 8 data lines DB0 to DB7. Three further control lines E, RS, and R/W are required. In the 4-bit mode data is transferred in two cycles of 4-bits each. The higher order bits (corresponding to DB4 to DB7 in 8-bit mode) are sent in the first cycle and the lower order bits (DB0 to DB3 in 8-bit mode) in the second cycle. Data transfer is complete after two 4-bit data transfers. It should be noted that two cycles are also required for the Busy Flag check. 4-bit operation is selected by instruction. See Figs 15, 16 and 17 for examples of bus protocol. In the 4-bit mode pins DB3 to DB0 must be left open-circuit. They are pulled up to VDD internally.
Set DDRAM address sets the DDRAM address (ADD in Table 3) into the Address Counter (binary A[6] to A[0). Data can then be written to or read from the DDRAM. Table 5 Hexadecimal address ranges ADDRESS 00 to 4F 00 to 0B and 0C to 4F 00 to 27 and 40 to 67 FUNCTION 1-line by 24 2-line by 12 2-line by 24
00 to 13, 20 to 33, 40 to 53 4-line by 12 and 60 to 73 9.9 Read busy flag and address
`Read busy flag and address' reads the Busy Flag (BF). When BF = logic 1 it indicates that an internal operation is in progress. The next instruction will not be executed until BF = logic 0, so BF should be checked before sending another instruction. At the same time, the value of the Address Counter expressed in binary A[6] to A[0] is read out. The Address Counter is used by both CGRAM and DDRAM and its value is determined by the previous instruction. 9.10 Write data to CGRAM or DDRAM
Writes binary 8-bit data D[7] to D[0] to the CGRAM or the DDRAM. Whether the CGRAM or DDRAM is to be written to is determined by the previous specification of CGRAM or DDRAM address setting. After writing, the address automatically increments or decrements by 1, in accordance with the entry mode. Only bits D0 to D4 of CGRAM data are valid, bits D5 to D7 are `don't care'.
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Philips Semiconductors
Product specification
LCD controller/driver
11 INTERFACE TO MICROCONTROLLER (I2C-BUS INTERFACE) 11.1 Characteristics of the I2C-bus 11.5 Acknowledge
PCF2104x
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 11.2 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. 11.3 Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). 11.4 System configuration
The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. 11.6 I2C-bus protocol
A device generating a message is a `transmitter', a device receiving a message is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves'.
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The I2C-bus configuration for the different PCF2104x READ and WRITE cycles is illustrated in Figs 22, 23 and 24.
handbook, full pagewidth
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.18 Bit transfer.
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24
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.19 Definition of START and STOP conditions.
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.20 System configuration.
handbook, full pagewidth
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement
MBC602
1
2
8
9
Fig.21 Acknowledgement on the
I2C-bus.
1997 Dec 16
25
Fig.22 Master transmits to slave receiver; WRITE mode.
handbook, full pagewidth
1997 Dec 16
acknowledgement from PCF2104x S
Philips Semiconductors
LCD controller/driver
S011101A0A1
0
CONTROL BYTE
A
DATA
A0
CONTROL BYTE
A
DATA
AP
slave address R/W
2n Co
0 bytes Co
1 byte
n
0 bytes
update data pointer
26
S 011101A0 0
MGC617
PCF2104x slave address
R/W
Product specification
PCF2104x
(1) Last data byte is a dummy byte (may be omitted).
Fig.23 Master reads after setting word address; write word address, set RS/RW; READ data.
handbook, full pagewidth
1997 Dec 16
acknowledgement from PCF2104x S
Philips Semiconductors
LCD controller/driver
S011101A0A1
0
CONTROL BYTE
A
DATA
A011
CONTROL
A
DATA
(1)
A
slave address R/W Co
2n
0 bytes Co
2 bytes
acknowledgement from PCF2104x
27
S
SLAVE ADDRESS
no acknowledgement from master
S A1A 0
DATA
A
DATA
1P
n bytes R/W
last byte update data pointer
MGC618
Product specification
PCF2104x
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
handbook, full pagewidth
acknowledgement from PCF2104x
acknowledgement from master
no acknowledgement from master
S
SLAVE ADDRESS
S A1A 0
DATA
A
DATA
1P
n bytes R/W
last byte update data pointer
MGC619
Fig.24 Master reads slave immediately after first byte; READ mode (RS previously defined).
1997 Dec 16
28
Fig.25 I2C-bus timing diagram; rise and fall times refer to VIL and VIH.
handbook, full pagewidth
1997 Dec 16
PROTOCOL START CONDITION (S) BIT 7 MSB (A7) BIT 6 (A6) BIT 0 LSB R/W ACKNOWLEDGE (A) STOP CONDITION (P) SDA
Philips Semiconductors
LCD controller/driver
29
SCL
t BUF
t LOW
tr
t HD;STA t HIGH
tf t/fSCL
MGA811 - 1
t SU;STO
Product specification
PCF2104x
Philips Semiconductors
Product specification
LCD controller/driver
12 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VLCD VI VO II IO Ptot PO Tstg supply voltage LCD supply voltage input voltage OSC, RS, R/W, E and DB0 to DB7 output voltage R1 to R32, C1 to C60 and VLCD DC input current DC output current total power dissipation power dissipation per output storage temperature PARAMETER MIN. -0.5 VDD - 11 VSS - 0.5 VLCD - 0.5 -10 -10 -50 - - -65
PCF2104x
MAX. +8.0 VDD VDD + 0.5 VDD + 0.5 +10 +10 +50 400 100 +150 V V V V mA mA mA
UNIT
IDD, ISS, ILCD VDD, VSS or VLCD current
mW mW C
13 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS Devices" ). 14 DC CHARACTERISTICS VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD - 3.5 to VDD - 9 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supplies VDD VLCD IDD IDD1 IDD2 supply voltage LCD supply voltage supply current external VLCD supply current 1 supply current 2 VDD = 5 V; VOP = 9 V; fosc = 150 kHz; Tamb = 25 C VDD = 3 V; VOP = 5 V; fosc = 150 kHz; Tamb = 25 C notes 1 and 6 note 2 note 1 2.5 VDD - 9 - - - - - - 200 200 6.0 VDD - 3.5 - 500 300 A A V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IDD3
supply current 3
-
150
200
A
ILCD VPOR
VLCD input current Power-on reset voltage level
- -
50 1.3
100 1.8
A V
1997 Dec 16
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
SYMBOL Logic VIL1 VIH1 VIL(osc) VIH(osc) Ipu IOL(DB) IOH(DB) IL1 I2C-bus SDA, SCL VIL2 VIH2 IL2 Ci IOL(SDA) LCD outputs RROW RCOL Vtol1 Notes
PARAMETER
CONDITIONS
MIN.
TYP. - - - - 0.15 - - -
MAX.
UNIT
LOW level input voltage pins E, RS, R/W, DB0 to DB7 and SA0 HIGH level input voltage pins E, RS, R/W, DB0 to DB7 and SA0 LOW level input voltage pin OSC HIGH level input voltage pin OSC pull-up current at pins DB0 to DB7, RS and R/W LOW level output current pins DB0 to DB7 HIGH level output current pins DB0 to DB7 leakage current pins OSC, E, RS, R/W, DB0 to DB7 and SA0 VI = VSS
VSS 0.7VDD VSS VDD - 0.1 0.04
0.3VDD VDD VDD - 1.5 VDD 1.00 - - +1
V V V V A mA mA A
VOL = 0.4 V; VDD = 5 V 1.6 VOH = 4 V; VDD = 5 V VI = VDD or VSS -1.0 -1
LOW level input voltage HIGH level input voltage leakage current input capacitance LOW level output current (SDA)
note 3 note 3 VI = VDD or VSS note 4
VSS 0.7VDD -1 -
- - - - -
0.3VDD VDD +1 7 -
V V A pF mA
VOL = 0.4 V; VDD = 5 V 3 note 5 note 5 note 6 - - -
row output resistance pins R1 to R32 column output resistance pins C1 to C60 bias voltage tolerance pins R1 to R32 and C1 to C60
1.5 3 20
3 6 130
k k mV
1. LCD outputs are open-circuit; inputs at VDD or VSS; V0 = VDD; bus inactive; internal or external clock with duty cycle 50% (IDD1 only). 2. Resets all logic when VDD < VPOR. 3. When the voltages are above or below the supply voltages VDD or VSS, an input current may flow; this current must not exceed 0.5 mA. 4. Tested on sample basis. 5. Resistance of output terminals (R1 to R32 and C1 to C60) with load current Iload = 150 A; VOP = VDD - VLCD = 9 V; outputs measured one at a time. 6. LCD outputs open-circuit.
1997 Dec 16
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
15 AC CHARACTERISTICS VDD = 2.5 to 6.0 V; VSS = 0 V; VLCD = VDD - 3.5 V to VDD - 9 V; Tamb = -40 C to + 85 C; unless otherwise specified. SYMBOL fFR fosc PARAMETER LCD frame frequency (internal clock) external clock frequency CONDITIONS note 1 MIN. 40 90 TYP. 65 150 MAX. 100 225 UNIT Hz kHz
Bus timing characteristics: Parallel Interface; notes 1 and 2 WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2104X) Tcy PWEH tASU tAH tDSW tHD Tcy PWEH tASU tAH tDHD tHD enable cycle time enable pulse width address set-up time address hold time data set-up time data hold time 500 220 50 25 60 25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 150 100 ns ns ns ns ns ns
READ OPERATION (READING DATA FROM PCF2104X TO MICROCONTROLLER) enable cycle time enable pulse width address set-up time address hold time data delay time data hold time 500 220 50 25 - 20 - - 4.7 4.7 4 4.7 4 - - 250 0 4 ns ns ns ns ns ns
Timing characteristics: I2C-bus interface; note 2 fSCL tSW tBUF tSU;STA tHD;STA tLOW tHIGH tr tf tSU;DAT tHD;DAT tSU;STO Notes 1. VDD = 5.0 V. 2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. SCL clock frequency tolerable spike width on bus bus free time set-up time for a repeated START condition start condition hold time SCL LOW time SCL HIGH time SCL and SDA rise time SCL and SDA fall time data set-up time data hold time set-up time for STOP condition 100 100 - - - - - 1 0.3 - - - kHz ns s s s s s s s ns ns s
1997 Dec 16
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Philips Semiconductors
Product specification
LCD controller/driver
16 TIMING DIAGRAMS
PCF2104x
handbook, full pagewidth
RS
VIH1 V IL1 t AS
VIH1 VIL1 t AH
R/W
V IL1 PW EH
VIL1 t AH VIL1 tH VIH1 VIL1
MLA798 - 1
E
VIH1 VIL1
VIH1 VIL1 t DSW VIH1 Valid Data VIL1 Tcy
DB0 to DB7
Fig.26 Parallel bus write operation sequence; writing data from microcontroller to PCF2104x.
handbook, full pagewidth
RS
VIH1 V IL1 t AS
VIH1 VIL1 t AH VIH1
R/W
VIH1
PW EH E VIL1 VIH1 VIH1
t AH VIL1 VIL1
t DDR DB0 to DB7 VOH1 VOL1 Tcy
t DHR VOH1 VOL1
MLA799 - 1
Fig.27 Parallel bus read operation sequence; reading data from PCF2104x to microcontroller. 1997 Dec 16 33
Philips Semiconductors
Product specification
LCD controller/driver
17 APPLICATION INFORMATION
PCF2104x
handbook, 4 columns
P20 P21 P22
RS 32 R/W E R1 to R32 to LCD 60
P80CL51
PCF2104x
C1 to C60 DB0 to DB7
MGC620
P10 to P17
8
Fig.28 Direct connection to 8-bit microcontroller; 8-bit bus.
handbook, 4 columns
P10 P11 P12
RS 32 R/W E R1 to R32 to LCD 60
P80CL51
PCF2104x
C1 to C60 DB4 to DB7
MGC621
P14 to P17
4
Fig.29 Direct connection to 8-bit microcontroller; 4-bit bus.
handbook, full pagewidth
VLCD 100 nF VDD 100 nF
VLCD VDD OSC
R7 to R16 R25 to R32 R1 to R8 R17 to R24 16
16
PCF2104x
V SS
2 x 24 CHARACTER LCD DISPLAY (SPLIT SCREEN) 60
MGC624
VSS
C1 to C60
60
DB0 to DB7 E
RS R/W
Fig.30 Typical application using parallel interface.
1997 Dec 16
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
handbook, full pagewidth
VLCD 100 nF VDD 100 nF VDD VDD V SS
VLCD VDD
R1 to R16
16
R17 to R24 OSC 16
2 x 24 CHARACTER LCD DISPLAY (SPLIT SCREEN) 60 60
PCF2104x
V SS C1 to C60 SA0
VDD
VLCD 100 nF VDD 100 nF
VLCD VDD OSC 16
R1 to R16
2 x 12 CHARACTER LCD DISPLAY
PCF2104x
V SS C1 to C60 SA0
MGC625
60
V SS
VSS
SCL SDA
MASTER TRANSMITTER PCF84C81
Fig.31 Application using I2C-bus interface.
1997 Dec 16
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Philips Semiconductors
Product specification
LCD controller/driver
17.1 8-bit operation, 2 x 12 display using internal reset 17.3 8-bit operation, 2 x 24 display
PCF2104x
Table 7 shows an example of a 1-line display in 8-bit operation. The PCF2104x functions must be set by the function set instruction prior to display. Since the display data RAM can store data for 80 characters, the RAM can be used for advertising displays when combined with display shift operation. Since the display shift operation changes the display position only and DDRAM contents remain unchanged. Display data entered first can be displayed when the `Return home' instruction is performed. 17.2 4-bit operation, 2 x 12 display using internal reset
For a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM address must be set after the eighth character is completed (see Table 8). It should be noted that both lines of the display are always shifted together, data does not shift from one line to the other. 17.4 I2C operation, 2 x 12 display
A control byte is required with most instructions (see Table 9). 17.5 Initializing by instruction
The program must set functions prior to 4-bit operation. Table 6 shows an example. When power is turned on, 8-bit operation is automatically selected and the PCF2104x attempts to perform the first write as an 8-bit operation. Since nothing is connected to DB0 to DB3, a rewrite is then required. However, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the functions (see Table 6 step 3). Thus, DB4 to DB7 of the function set are written twice.
If the power supply conditions for correctly operating the internal reset circuit are not met, the PCF2104x must be initialized by instruction. Tables 10 and 11 show how this may be performed for 8-bit and 4-bit operation.
1997 Dec 16
36
Philips Semiconductors
Product specification
LCD controller/driver
Table 6 STEP 1 2 4-bit operation, 1-line display example; using internal reset INSTRUCTION Power supply on (PCF2104x is initialized by the internal reset circuit). Function set: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 0 3 Function set: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 0 RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0 4 Display on/off control: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0 RS = 0; R/W = 0; DB7 = 1; DB6 = 1; DB5 = 1; DB4 = 0 5 Entry mode set: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0 RS = 0; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 1; DB4 = 0 6 Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1 RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 1; DB4 = 0 P_ _ Turns on display and cursor. DISPLAY OPERATION Initialized. No display appears.
PCF2104x
Sets to 4-bit operation. In this instance operation is handled as 8-bits by initialization and only this instruction completes with one write. Sets to 4-bit operation, selects 2 x 12 display. 4-bit operation starts from this point and resetting is needed.
Entire display is blank after initialization.
Sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DD/CGRAM. Display is not shifted.
Writes `P'. The DDRAM has already been selected by initialization at power-on. The cursor is incremented by 1 and shifted to the right.
1997 Dec 16
37
1997 Dec 16 38
Philips Semiconductors
Table 7 STEP 1 2
8-bit operation, 1-line display example; using internal reset (character set `A')
LCD controller/driver
INSTRUCTION Power supply on (PCF2104x is initialized by the internal reset function). Function set: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0 Display mode on/off control: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 1; DB1 = 1; DB0 = 0 Entry mode set: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 1; DB1 = 1; DB0 = 0 Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0 Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 1; DB4 = 1; DB3 = 1; DB2 = 0; DB1 = 0; DB0 = 0 _
DISPLAY
OPERATION Initialized. No display appears. Sets to 8-bit operation, selects 2 x 12 display.
3
Turns on display and cursor. Entire display is blank after initialization. Sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DD/CGRAM. Display is not shifted. Writes `P'. The DDRAM has already been selected by initialization at power-on. The cursor is incremented by 1 and shifted to the right. Writes `H'.
4
_
5
P_
6
PH_
7
| | | Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 0; DB1 = 1; DB0 = 1 Entry mode set: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 1; DB1 = 1; DB0 = 1 Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 0; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0 Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 1; DB1 = 0; DB0 = 1 PHILIPS_ Writes `S'.
8
9
PHILIPS_
Sets mode for display shift at the time of write.
10
HILIPS _
Writes space.
11
ILIPS
M_
Writes `M'.
Product specification
PCF2104x
12
| | |
1997 Dec 16 39
Philips Semiconductors
STEP 13
INSTRUCTION Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 1; DB1 = 1; DB0 = 1 Cursor or display shift: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0 Cursor or display shift: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0 Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 0; DB1 = 1; DB0 = 1 Cursor or display shift: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 1; DB3 = 1; DB2 = 1; DB1 = 0; DB0 = 0 Cursor or display shift: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 1; DB1 = 0; DB0 = 0 Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 1; DB1 = 0; DB0 = 1
DISPLAY MICROKO Writes `O'.
OPERATION
LCD controller/driver
14
MICROKO
Shifts only the cursor position to the left.
15
MICROKO
Shifts only the cursor position to the left.
16
ICROCO
Writes `C' correction. The display moves to the left.
17
MICROCO
Shifts the display and cursor to the right.
18
MICROCO_
Shifts only the cursor to the right.
19
ICROCOM_
Writes `M'.
20
| | | Return home: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 0; DB1 = 1; DB0 = 0 PHILIPS M Returns both display and cursor to the original position (address 0).
21
Product specification
PCF2104x
1997 Dec 16 40
Philips Semiconductors
Table 8 STEP 1 2
8-bit operation, 2-line display example; using internal reset
LCD controller/driver
INSTRUCTION Power supply on (PCF2104x is initialized by the internal reset function). Function set: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1; DB3 = 1; DB2 = 0; DB1 = 0; DB0 = 0 Display on/off control: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 1; DB1 = 1; DB0 = 0 Entry mode set: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 1; DB1 = 1; DB0 = 0 Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0 _
DISPLAY
OPERATION Initialized. No display appears. Sets to 8-bit operation, selects 2 x 24 display
3
Turns on display and cursor. Entire display is blank after initialization. Sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the CG/DDRAM. Display is not shifted. Writes `P'. The DDRAM has already been selected by initialization at power-on. The cursor is incremented by 1 and shifted to the right. | | |
4
_
5
P_
6
7
Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 0; DB1 = 1; DB0 = 1 Set DDRAM address: RS = 0; R/W = 0; DB7 = 1; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0 Write data to CGRAM/ DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 1; DB1 = 0; DB0 = 1
PHILIPS_
Writes `S'.
8
PHILIPS _ PHILIPS M_ | | |
Sets DDRAM address to position the cursor at the head of the 2nd line. Writes `M'.
9
10
Product specification
11
Write data to CGRAM/ DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 1; DB1 = 1; DB0 = 1 Write data to CGRAM/ DDRAM: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 1; DB1 = 1; DB0 = 1
PHILIPS MICROCO_ PHILIPS MICROCO_
Writes `O'.
PCF2104x
12
Sets mode for display shift at the time of write.
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Philips Semiconductors
STEP 13
INSTRUCTION Write data to CGRAM/ DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 1; DB1 = 0; DB0 = 1
DISPLAY HILIPS ICROCOM_ | | |
OPERATION Writes `M'. Display is shifted to the left. The first and second lines shift together.
LCD controller/driver
14
15
Return home: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 0; DB1 = 1; DB0 = 0
PHILIPS MICROCOM
Returns both display and cursor to the original position (address 0).
Product specification
PCF2104x
1997 Dec 16 42
Philips Semiconductors
Table 9 STEP 1 2
Example of I2C-bus operation; 1-line display (using internal reset, assuming SA0 = VSS; note 1) I2C-BUS BYTE I2C-bus start Slave address for write: SA6 = 0; SA5 = 1; SA4 = 1; SA3 = 1; SA2 = 0; SA1 = 1; SA0 = 0; R/W = 0; Ack = 1 Send a control byte for function set: Co = 0; RS = 0; R/W = 0; Ack = 1 Function set: DB7 = 0; DB6 = 0; DB5 = 1; DB4 = X; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0; Ack = 1 Display on/off control: DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 1; DB1 = 1; DB0 = 0; Ack = 1 Entry mode set: DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 1; DB1 = 1; DB0 = 0; Ack = 1 I2C-bus start Slave address for write: SA6 = 0; SA5 = 1; SA4 = 1; SA3 = 1; SA2 = 0; SA1 = 1; SA0 = 0; R/W = 0; Ack = 1 Send a control byte for write data: Co = 0; RS = 1; R/W = 0; Ack = 1 Write data to DDRAM: DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0; Ack = 1 Write data to DDRAM: DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 0; DB1 = 0; DB0 = 0; Ack = 1 _ DISPLAY OPERATION Initialized. No display appears. During the acknowledge cycle SDA will be pulled-down by the PCF2104x. Control byte sets RS and R/W for following data bytes. Selects 1-line display; SCL pulse during acknowledge cycle starts execution of instruction. Turns on display and cursor. Entire display shows character Hex 20 (blank in ASCII-like character sets). Sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DDRAM or CGRAM. Display is not shifted. For writing data to DDRAM, RS must be set to 1. Therefore a control byte is needed.
LCD controller/driver
3 4
5
6
_
7 8
_ _
9 10
_ P_ Writes `P'. The DDRAM has been selected at power-up. The cursor is incremented by 1 and shifted to the right. Writes `H'.
11
PH_
12 to 15
| | | | Write data to DDRAM: DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 0; DB1 = 1; DB0 = 1; Ack = 1 PHILIPS_ Writes `S'.
Product specification
PCF2104x
16
1997 Dec 16 43
Philips Semiconductors
STEP 17 18 19 (optional (as step 8) I2C-bus stop)
I2C-BUS BYTE I2C-bus
DISPLAY
OPERATION
LCD controller/driver
start + slave address for write PHILIPS_ PHILIPS_ PHILIPS Sets DDRAM address 0 in Address Counter. (Also returns shifted display to original position. DDRAM contents unchanged). This instruction does not update the Data Register (DR). DDRAM content will be read from following instructions. The R/W has to be set to 1 while still in I2C-bus write mode. During the acknowledge cycle the content of the DR is loaded into the internal I2C-bus interface to be shifted out. In the previous instruction neither a `Set address' nor a `Read data' has been performed. Therefore the content of the DR was unknown. 8 x SCL; content loaded into interface during previous acknowledge cycle is shifted out over SDA. MSB is DB7. During master acknowledge content of DDRAM address 01 is loaded into the I2C-bus interface. 8 x SCL; code of letter `H' is read first. During master acknowledge code of `I' is loaded into the I2C-bus interface. No master acknowledge; After the content of the I2C-bus interface register is shifted out no internal action is performed. No new data is loaded to the interface register, Data Register (DR) is not updated, Address Counter (AC) is not incremented and cursor is not shifted.
Control byte: Co = 1; RS = 0; R/W = 0; Ack = 1 Return home: DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 0; DB1 = 1; DB0 = 0; Ack = 1 Control byte for read: Co = 0; RS = 1; R/W = 1; Ack = 1 I2C-bus start Slave address for read: SA6 = 0; SA5 = 1; SA4 = 1; SA3 = 1; SA2 = 0; SA1 = 1; SA0 = 0; R/W = 1; Ack = 1
20
PHILIPS
21 22
PHILIPS PHILIPS
23
Read data: 8 x SCL + master acknowledge; note 2: DB7 = X; DB6 = X; DB5 = X; DB4 = X; DB3 = X; DB2 = X; DB1 = X; DB0 = X; Ack = 1 Read data: 8 x SCL + master acknowledge; note 2: DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 0; DB1 = 0; DB0 = 0; Ack = 0 Read data: 8 x SCL + no master acknowledge; note 2: DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 0; DB1 = 0; DB0 = 1; Ack = 1
PHILIPS
24
PHILIPS
25
PHILIPS
26 Notes
I2C stop
PHILIPS Product specification
PCF2104x
1. X = don't care. 2. SDA is left at high-impedance by the microcontroller during the READ acknowledge.
1997 Dec 16 44
Philips Semiconductors
Table 10 Initialization by instruction, 8-bit interface (note 1)
LCD controller/driver
STEP Power-on or unknown state | Wait 2 ms after VDD rises above VPOR | RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1; DB3 = X; DB2 = X; DB1 = X; DB0 = X | Wait 2 ms | RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1; DB3 = X; DB2 = X; DB1 = X; DB0 = X | Wait more than 40 s | RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1; DB3 = X; DB2 = X; DB1 = X; DB0 = X | | RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1; DB3 = N; DB2 = M; DB1 = X; DB0 = 0 RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 0; DB1 = 0; DB0 = 0 RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 1 RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 1; DB1 = I/D; DB0 = S | Initialization ends Note 1. X = don't care.
DESCRIPTION
BF cannot be checked before this instruction. `Function set' (interface is 8-bits long).
BF cannot be checked before this instruction.`Function set' (interface is 8-bits long).
BF cannot be checked before this instruction. `Function set' (interface is 8-bits long). BF can be checked after the following instructions. When BF is not checked, the waiting time between instructions is the specified instruction time (see Table 3). `Function set' (interface is 8-bits long). Specify the number of display lines. `Display off'. `Clear display'. `Entry mode set'.
Product specification
PCF2104x
1997 Dec 16 45
Philips Semiconductors
Table 11 Initialization by instruction, 4-bit interface. Not applicable for I2C-bus operation
LCD controller/driver
STEP Power-on or unknown state | Wait 2 ms after VDD rises above VPOR | RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1 | Wait 2 ms | RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1 | Wait 40 s | RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1 | | RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 0 RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 0 RS = 0; R/W = 0; DB7 = N; DB6 = M; DB5 = 0; DB4 = 0 RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0 RS = 0; R/W = 0; DB7 = 1; DB6 = 0; DB5 = 0; DB4 = 0 RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0 RS = 0; R/W = 0; DB7 = 1; DB6 = 0; DB5 = 0; DB4 = 0 RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0 RS = 0; R/W = 0; DB7 = 0; DB6 = 1; DB5 = I/D; DB4 = S | Initialization ends
DESCRIPTION
BF cannot be checked before this instruction. `Function set' (interface is 8-bits long).
BF cannot be checked before this instruction. `Function set' (interface is 8-bits long).
BF cannot be checked before this instruction. `Function set' (interface is 8-bits long). BF can be checked after the following instructions. When BF is not checked, the waiting time between instructions is the specified instruction time (see Table 3). `Function set' (set interface to 4-bits long). Interface is 8-bits long. `Function set' (interface is 4-bits long). Specify number of display lines and voltage generator characteristic. `Display off'. `Clear display'. `Entry mode set'.
Product specification
PCF2104x
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
handbook, full pagewidth
DISPLAY LAYOUT: COLUMNS C1 15 46 60 PCF2104x column output numbers
1
31 DOT MATRIX LCD
60
LCD column numbers
C16
45
PCF2104x column output numbers
DISPLAY LAYOUT: ROWS R8 to R1 R9 to R16
MGC623
R17 to R24
R32 to R25
Fig.32 Example of 4 x 12 display layout (PCF2104x). 1997 Dec 16 46
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
handbook, full pagewidth
display glass
dot matrix
COLUMN LAYOUT
1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
ROW LAYOUT
1 to 8
16 to 9
MLB898
2 lines by 12 characters display
Fig.33 Display example (PCF2104x); 2 lines by 12 characters.
1997 Dec 16
47
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
handbook, full pagewidth
R1 R8
PCF2104x CHIP-ON-GLASS
R9 R16
R17 R24
4 LINE BY 12 CHARACTER
C1
R25 R32
2104
R9 C60
MGC626
SCL SDA
VSS VDD VLCD
Fig.34 Chip-on-glass application.
1997 Dec 16
48
Philips Semiconductors
Product specification
LCD controller/driver
18 BONDING PAD LOCATIONS
PCF2104x
R13
R10
C11
C13
C14
C15
C18
C21
R14
C12
C19
R11
C10
R12
R9
C2
C3
C5
C4
C1
C6
C7
C8
86 85 84 83 82 81
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59
C9
handbook, full pagewidth
C16
C17
C20
C22
R15 R16 R25 R26 R27 R28 R1 R2 R3 R4 SCL E RS 5.63 mm
87 88 89 90 91 92 93 94 95 96 97 98 99
58 57 56 55 54 53 52 51 50 49 48 47 46 45
C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53
R/W 100 T1 101 DB7 102 DB6 103 DB5 104 DB4 105 DB3 106 DB2 107 DB1 108 DB0 109 SDA 110
x 0 0 y
44 43 42 41 40 39
PCF2104x
38 37 36 35 34 33 32 31 30 29
VLCD 111
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
28
R5
R32
R30
R23
R20
R18
R17
C60
C57
OSC
VSS
SA0
R31
R19
C56
R24
R21
R29
R22
VDD
5.10 mm
C59
C58
C55
C54
R8
R7
R6
MGC628
Chip dimensions: approximately 5.10 x 5.63 mm. Gold bump dimensions: approximately 89 x 89 x 25 m.
Fig.35 Bonding pad locations.
1997 Dec 16
49
Philips Semiconductors
Product specification
LCD controller/driver
Table 12 Bonding pad locations (dimensions in m). All x/y coordinates are referenced to centre of chip, see Fig.35 SYMBOL OSC VDD SA0 VSS R8 R7 R6 R5 R32 R31 R30 R29 R24 R23 R22 R21 R20 R19 R18 R17 C60 C59 C58 C57 C56 C55 C54 C53 C52 C51 C50 C49 C48 C47 C46 C45 C44 C43 1997 Dec 16 PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 x -2184.5 -2024.5 -1864.5 -1704.5 -1339 -1179 -1019 -859 -699 -539 -379 -219 -59 101 261 421 581 741 901 1061 1221 1381 1541 1701 1861 2021 2181 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 y -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2445 -2285 -2125 -1965 -1805 -1645 -1485 -1325 -1165 -1005 -845 50 SYMBOL C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 PAD 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 x 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2185 2025 1865 1705 1545 1385 1225 1065 905 745 585 425 265 105 -55 -215 -375 -535
PCF2104x
y -685 -525 -365 -205 -45 115 275 435 595 755 915 1075 1235 1395 1555 1715 1875 2035 2195 2355 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
SYMBOL C4 C3 C2 C1 R9 R10 R11 R12 R13 R14 R15 R16 R25 R26 R27 R28 R1 R2 R3 R4 SCL E RS R/W T1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SDA VLCD RECPAT `F' RECPAT `C' RECPAT `C'
PAD 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111
x -695 -855 -1015 -1175 -1385 -1545 -1705 -1865 -2025 -2185 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2327.5 -2027.5 1982.5
y 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2308 2148 1988 1828 1668 1508 1348 1188 1028 868 632 472 312 142 -34 -233 -393 -668 -828 -1103 -1263 -1538 -1698 -1933 -2453 2427.5 -2512.5 2297.5
1997 Dec 16
51
Philips Semiconductors
Product specification
LCD controller/driver
19 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCF2104x
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 20 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 21 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Dec 16
52
Philips Semiconductors
Product specification
LCD controller/driver
NOTES
PCF2104x
1997 Dec 16
53
Philips Semiconductors
Product specification
LCD controller/driver
NOTES
PCF2104x
1997 Dec 16
54
Philips Semiconductors
Product specification
LCD controller/driver
NOTES
PCF2104x
1997 Dec 16
55
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580/xxx France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2870, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417067/1200/04/pp56
Date of release: 1997 Dec 16
Document order number:
9397 750 02924

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